Five-Stage CPU Emulator
A C implementation of a pipelined processor with forwarding, instruction and data caches, and LRU replacement.
Work / Selected projects
I use projects to understand the full path from an abstraction to its real behavior. These case studies cover processor architecture, infrastructure, and robotics.
01 / Featured
A C implementation of a pipelined processor with forwarding, instruction and data caches, and LRU replacement.
A maintained Debian environment for containerized services, private administration, public routing, and repeatable deployment.
An in-progress tracked rover integrating ROS 2, micro-ROS, embedded motor control, LiDAR, and a developing SLAM workflow.
02 / Archive
2025
A C allocator using an address-ordered explicit free list, first-fit placement, coalescing, and eight size bins.
Private source